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Fetch/execute cycle

The term fetch/execute is used to describe the process of sending and receiving data to/from the processor and memory (whether it be RAM (main memory) or cache).

When a memory read operation occurs;

  • data is read from a memory address
  • it is then taken to the processor

When a memory write operation occurs:

  • data is taken from the processor
  • it is then written to the memory

What happens during the fetch/execute cycle?

During the fetch/execute cycle the , data bus and address bus are all in use:

  • the control unit will:
    • dictate the clock speed of the fetch/execute cycle
    • activate either the read or write line
  • the address bus will hold the address that is being accessed in main memory
  • the data bus will either transfer the data contained in the memory address to the processor, or will transfer data from the processor to the memory address

The control unit clock line is active at all times, setting the pulse/pace of the fetch/execute cycle.

Fetch/Execute – Memory Read

  1. MAR (Memory Address Register) sets up the address bus with the relevant memory location to be read from
  2. The control unit read line is activated
  3. The contents of the address held on the address bus are placed on the data bus
  4. The data bus transfers the data from memory to the MDR (Memory Data Register)

Fetch/Execute – Memory Write

  1. MAR (Memory Address Register) sets up the address bus with the relevant memory location to be written to
  2. MDR (Memory Data Register) passes the data to be written to the data bus
  3. The control unit write line is activated
  4. Data bus transfers the data to the memory location specified on the address bus